Testing semiconductor devices can prevent the potentially considerable cost of packaging faulty integrated circuit (IC) die in IC products such as processors. Nevertheless, it is not always feasible to use all test types on a given IC die due to considerations including design cost, product cost or tester memory limits. Thus, the level of test coverage for IC products can be an economic decision impacted by a number of different factors.
Test coverage, or fault coverage, represents a percentage of a type of fault model detectable during testing of an IC die. A high fault coverage, therefore, can be valuable during manufacturing test. High fault coverage numbers, however, usually require very careful design-for-test (DFT) implementations, large amounts of test generation time and pattern volumes, and long test times. Each of these can be costly and can prove intractable due to test resource limitations such as tester memory.
Different mathematical models have been used to assist in determining the feasibility of performing a specific test of interest for an IC die. The different mathematical models, such as the Williams and Brown Model, can be used for estimating test escape rates for a test of interest as a function of yield and fault coverage. A test escape rate, also known as time zero (T0) defective parts per million (DPPM), represents the risk that a chip (i.e., an IC die) will not function when tested as part of a multi-chip module (e.g., an IC product). A test escape rate of a proposed test is often referred to as a defect level and is specified in terms of DPPM.
The Williams and Brown model, in addition to other conventional models, is a unidimensional model that generates a test escape estimate for a single test type while neglecting other tests. Typical test programs for IC products, however, include multiple tests of different types having overlapping failing unit detections. For example, IC manufacturers may employ tests which are either sourced from automatic test pattern generation (ATPG) software or are fault graded using fault simulation tests including but not limited to: stuck-at tests, transition tests and IDDQ tests. What would be useful in the art is a method or system that provides an improved model which can estimate the return on investment (ROI) for conventional test generation efforts in order for product designers and test engineers to perform trade-off analysis that can assist in the design of integrated circuits.